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Technote 1055

July 1996

From the first to second generation Power Macintosh computers, Apple has increased the total amount of expandable memory, and has transitioned memory expansion from 72-pin SIMMs to 168-pin DIMMs. Unfortunately, as with earlier Macintosh computers, the transition to 168-pin DIMMs for memory expansion has not dampened the endless flow of memory questions from developers, system integrators, and end users.

What tends to drive the confusion is the fact there are dozens of companies that supply memory modules which, in turn, use DRAM devices manufactured by a number of different semiconductor vendors. As a consequence, you end up with multiple combinations of all sizes and configurations of SIMMs and DIMMs.

This Technote will answer frequently asked questions about DIMMs, and provide in-depth details in an effort to head off those unasked questions by raising the awareness of the reader.

This Technote is aimed at support engineers, VARs, system integrators, and third-party developers. If you're already designing SIMM and DIMM memory modules, much of this information may already be known. A glossary of commonly used terms and abbreviations is provided at the end of this Note.

As we advance the Macintosh platform, this Technote will be revised to reflect the changes that are driven by the ever-increasing need to have higher memory throughput.

CONTENTS

• Some Frequently Asked Questions (FAQs)
  
• Commonly Used Terms and Abbreviations
  

Some Frequently Asked Questions (FAQs)

Why has Apple transitioned memory expansion from 72-pin SIMMs to 168-pin DIMMs for PowerMac computers?

• a wider 64 bit data path
• higher memory capacity
• greater flexibility because systems do not require DIMMs to be installed in complementary pairs.

Why do SIMMs need to be installed in complementary pairs, when DIMMs can be added on a per module basis?

To span the PowerPC 64 bit data bus, SIMMs need to be installed in complimentary pairs (i.e., in parallel). DIMMs, with their 64 bit data bus, can be installed individually in second generation Power Macintosh computers.

The only exception to this are some entry-levels Power Macintosh computers, such as the Power Macintosh 5200/75 LC, which incorporate a PowerPC 603 processor configured with a 32 bit bus. In such computers, SIMMs are used for memory expansion and not installed in identical pairs.

How does the PowerPC address memory?

Figure 1 illustrates a 32 bit address bus and a 64 bit data bus. Although the PowerPC has 4G of address space, only a portion of the 4G is allocated for main memory (DRAM memory). For example, the total RAM expansion on entry-level Macs can be as much as 136 Mbytes, while RAM expansion on Power Mac 9500 can be as much as 1.5G. The remaining portion of the address space is allocated for system ROM, PCI cards, system control, etc.

Figure 1 A PowerPC system bus

Data is transferred between the PowerPC and main memory via the 64 bit data bus by memory reads or memory writes.

There are two types of memory transactions: single -and four-beat transfers. A single-beat memory transaction reads or writes between one to 8 bytes of data. (Equating 8 bytes to 64 bits and noting that the data bus is 64 bits wide, the PowerPC can read or write eight bytes in a single memory operation.) A four-beat memory transaction reads or writes a cache block of 32 bytes to or from memory. Each of the four beats encompasses 8 bytes.

What's important to understand is that the memory bus is 64 bits wide and up to 8 bytes can be transferred in a single memory operation.

What is memory interleaving and what advantage does it provide?

Memory interleaving provides higher bandwidth (MBytes per second) between the PowerPC microprocessor and main memory. It also provides a significant performance boost, increasing the execution speed of memory-intensive programs. How much faster depends on the program's software architecture and whether an L2 cache is present.

How is memory interleaving enabled?

What speed SIMMs and DIMMs are required for PowerMac computers?

Can faster speed memory modules be used in Power Macintosh computers and will they increase system performance, i.e., 60 nsec instead of 70 nsec modules for a performance increase of 10 - 15 percent?

Note:

Apple recommends that for memory expansion that you stay with the speed specified for the computer. Although faster devices most likely will work, keep in mind that these are untested configurations.

Using an example of a 4M x 4 (16 MBit, 11/11) DRAM device, Figure 2 illustrates a basic timing diagram of how the device is addressed for a typical read cycle. Addressing a 4M address space requires 22 address inputs. DRAM devices have their address inputs multiplexed by row and column addresses (in this example: 11 row and 11 column addresses, noted by "11/11"). The memory controller delivers the row and column address at different times, and drives signals referred to as RAS and CAS to strobe in the respective addresses. Note that the access time from the beginning of the address cycle to valid data out (measured from RAS) is 70 nsec.

DRAM access time directly correlates to the speed specification for SIMM and DIMM memory modules; 60, 70, and 80 nsec are common speeds required by today's typical Macintosh and PC CPUs. Access time is specified as a maximum value.

Figure 2 A basic timing diagram showing how the device is addressed for a typical read cycle

Can different speed memory modules be intermixed, i.e., 60 and 70 nsec modules in a PowerMac that is specified at 70 nsec?

What does refresh rate or count refer to (e.g., 1K, 2K, or 4K)?

Data stored in DRAM devices is volatile. To maintain data integrity, DRAM requires a power source and continuous refreshing.

DRAMs are specified at different refresh rates that may or may not be compatible with a particular PC model. Macintosh computers are compatible with widely available DRAM devices.

Table 1 lists three common 16 MBit DRAM devices used to construct SIMMs or DIMMs.

Table 1. Refresh vs. addressing

Note:

4M x 4 refers to a DRAM device with an address space of 4M locations, each containing a data word 4 bits wide. (4M x 4 equals 16 Mbits; DRAM devices are usually referred to by size [total number of bits].)

How do PowerMac computers provide continuous refreshing?

A 16 MBit (11/11) device with an 11 row address - referred to as a 2K refresh part - requires all row address combinations (2048) to be accessed every 32 msec. A 4K refresh device (12/10) requires 64 msec to refresh all row addresses. DRAM row addresses are refreshed by the Refresh Address Counter, which is triggered by a CAS before RAS refresh cycle.

The importance, therefore, lies less in whether or not a Macintosh CPU supports 1K, 2K, and/or 4K refresh DRAM parts than whether the Macintosh Memory Controller and DRAM devices have compatible addressing schemes, and whether the DRAM devices are compatible with CAS before RAS refresh cycles every 15.6 usec. For further details, refer to the appropriate Developer Note for the particular CPU.

How are different sized SIMMs and DIMMs -- 16 Mbytes, 32 Mbytes, etc. -- designed with different types of DRAM devices, such as 4M x 4, 2M x 8, and 1M x 16 parts?

Remembering that DIMMs and SIMMs have a 64 bit and 32 bit wide data bus, respectively, the following examples can be applied to SIMM modules by using half the number of devices to span 32 bits.

Figure 3 shows a 32 Mbyte DIMM using 4M x 4 devices in a single bank design. SIMM and DIMM memory modules accommodate one or two memory banks. Two bank modules will be discussed later.

When examining the layout shown in Figure 3, note the following:

• a single bank implementation;
• the memory is laid out to span 64 bits, so 4M x 4 devices require 16 parts per bank;
• the addressing is common across all DRAM on the module and is multiplexed via RAS and CAS singles, as noted by Control;
• the module has a density of 4M x 64 (address space of 4M by 64 bits wide), or 32 Mbytes.

Note:

Macintosh computers will size and determine the addressing mode (e.g., 4M x 4, 2M x 8, etc.) of memory modules at system startup.

Figure 3 A 4M x 64 DIMM module or 32 Mbyte device, constructed with 4M x 4 DRAM devices in single bank layout

Figure 4 shows a 16 Mbyte DIMM using 2M x 8 devices in a single bank. You may be asking yourself: if both 4M x 4 and 2M x 8 parts are considered 16 Mbit devices and both examples are single bank designs, why is Figure 3's design 32 Mbytes and Figure 4's design 16 Mbytes? Since the data path of a 2M x 8 device is 8 bits wide, rather than 4 bits wide -- as for 4M x 4 parts -- it requires half the number of devices to span across 64 bits.

Note:

Figure 4 uses 8 devices and Figure 3 uses 16. Figure 4 thus has a module density of 2M x 64, or 16, Mbytes.

Figure 4 A 2M x 64 DIMM module or 16 Mbyte device, constructed with 2M x 8 DRAM devices in single bank layout

Figure 5 shows a 16 Mbyte DIMM using 1M x 16 devices in a two bank design. What's important to note for this particular design is the following:

• There are two separate memory banks;
• each bank contains four devices - spanning 64 bits
• both banks have common address and data buses

Figure 5 A 32 Mbyte DIMM using 1M x 16 devices in a two bank design.

Do Macintosh computers support composite memory modules?

Can memory modules with different refresh rates or counts be intermixed?

DIMMs with different supported refresh rates can be intermixed. But if it's intended to enable memory interleaving, DIMMs with different refresh rates may or may not have DRAM devices with same addressing modes.

Note:

DRAM devices require the same addressing mode to enable interleaving. Please refer to the appropriate Developer Note, located on the Developer CD, Reference Library edition.

What is EDO memory and do Macintosh computers support it?

EDO DRAM is a superset of conventional (also called Fast Page Mode) DRAM. This means that an EDO DRAM can be used in place of a Fast Page Mode DRAM, although unless the memory controller is designed to utilize the faster EDO timing, the memory performance will be the same as Fast Page Mode.

Power Macintosh computers do not yet support the extended data out timing that EDO DRAM devices can provide. If memory modules with EDO DRAM are designed to be fully compatible with standard Fast Page Mode DRAM, however, they should function properly. (Be sure to check with the SIMM or DIMM manufacturer and specify the Macintosh model.)

In the future, PowerMacs will support the extended data out timing, taking full advantage of EDO DRAM devices.

What is parity memory and do Power Macintosh computers support it?

Apple's newly-introduced Network Server 500 and 700 products are the only computers that support parity memory; all other Power Macintosh Desktop, Tower, and PowerBook computers do not. Parity memory modules add one parity bit to each byte. Thus, a 64 bit DIMM -- eight bytes -- expands from 64 bits to 72 bits wide.

What is ECC memory and do Macintosh computers support it?

Commonly Used Terms and Abbreviations

Mbytes

millions of bytes

GBytes

giga (one thousand million) of bytes

32 bits

data path or data storage unit thirty two bits wide

64 bits

data path or data storage unit sixty four bits wide

1M x 16

DRAM device with one million 16 bit wide data storage units

2M x 8

DRAM device with two million 8 bit wide data storage units

4M x 4

DRAM device with four million 4 bit wide data storage units

usec

Microseconds, or one millionth of a second

msec

Milliseconds, or one thousandth of a second

nsec

Nanoseconds, or one thousandth of a millionth of a second

memory modules

generic term referring to either 72-pin SIMM or 168-pin DIMM modules

first generation Power Macintosh

NuBus I/O expansion

second generation Power Macintosh

PCI I/O expansion

CAS

Column Address Strobe

RAS

Row Address Strobe

Further Reference

• Developer Notes for specific Macintosh models and JEDEC Standard 21-C

Acknowledgments